In a makefile, how do I execute a command on each file name in variable?

I know I am doing it wrong, but I can't figure out how to organize this makefile. I define my util source files, and use some functions to define the .o files from them here:

UTIL_SRC = utils/src/foo.cpp utils/src/bar.cpp utils/src/baz.cpp

UTIL开发者_开发百科_OBJS = $(patsubst utils/src/%.cpp,utils/obj/%.o,$(UTIL_SRC))

This is the target that I use these files for:

lib : lib/libutils.a

lib/libutils.a : $(UTIL_OBJS)
    rm -f lib/libutils.a
    ar -c -q lib/libutils.a $(UTIL_OBJS)

Then, when I get to the rule to compile these babies, I would love to just have one command that would iterate through each UTIL_OBJS file and each UTIL_SRC file. Instead I have resorted to this monstrosity, which defeats the purpose of storing them in variables.

$(UTIL_OBJS) : $(UTIL_SRC)
    g++ $(UTIL_FLAGS) utils/src/foo.cpp -o utils/obj/foo.o
    g++ $(UTIL_FLAGS) utils/src/bar.cpp -o utils/obj/bar.o
    g++ $(UTIL_FLAGS) utils/src/baz.cpp -o utils/obj/baz.o

Can I condense this down to one line? How? Thanks, great ones!

It's usually easier to work with implicit rules. There are a lot of predefined ones, where you'll only need to specify variables.

CXX=g++
CXXFLAGS=$(UTIL_FLAGS)

Then you need to define an executable, like this

myutil: $(UTIL_OBJS)

Since you're not storing your objects in the same directory, you'll need to specify a new implicit rule as well though (otherwise, we'd be done now).

utils/obj/%.o: utils/obj/%.cpp

% is a pattern-match, it'll match the same text on both left and right side, so this rule will make foo.o out of foo.cpp. Try if that'll work without the command (it might have grabbed that from another rule, I'm not sure), otherwise let it say:

utils/obj/%.o: utils/obj/%.cpp
    $(CXX) $(CXXFLAGS) -o $@ $^

$@ is the target of the rule (e.g. foo.o), and $^ is all files on the right hand side. I'm writing this off the top of my head, without the possibility to test it, so please let me know how it turned out.. :)

To make it even more elegant, you can include a dependency file

include .depend

If you're running GNU make, it'll try to make the .depend file if it can't find it (with old school make, you need to create it yourself first, it can be just a dummy though, if you'd like to manage it through the makefile)

.depend: $(UTIL_SRC)
    $(CXX) -MM -o $@ $^

The dependency file will contain lines for each .cpp file, telling make what header files it needs, which will allow make to recompile the necessary files when you change something. This doesn't help with your original question though, just thought it might come in handy.

EDIT:
As a response to your edit. You could probably drop the commands for creating the .a-file as well, that too is already available as an implicit rule. Not sure exactly how it works though, haven't used it much. I do know that there are a bunch of quirks in make for dealing with .a(rchive?)-files.

I think you could use this:

$(UTIL_OBJS) : $(UTIL_SRC)
    g++ $(UTIL_FLAGS) $(@ : .o = .cpp)  -o $@ 

again, I'm not quite sure... especialy about the $(@ : .cpp = .o) part