Implicit Memory Barriers

let's say i have variables A, B and C that two threads (T1, T2) share.

i have the f开发者_Go百科ollowing code:

//T1  
//~~

A = 1;  
B = 1;  
C = 1;

InterlockedExchange(ref Foo, 1);

//T2  (executes AFTER T1 calls InterlockedExchange)  
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

InterlockedExchange(ref Bar, 1);

WriteLine(A);  
WriteLine(B);  
WriteLine(C);  

Question:

does calling InterlockedExchange (implicit full fence) on T1 and T2, gurentess that T2 will "See" the write done by T1 before the fence? (A, B and C variables), even though those variables are not plance on the same cache-line as Foo and Bar?

Yes. A memory fence is not variable specific; it causes completion of all loads and stores issued prior to the fence by the calling thread.

I may be wrong, but I suspect the fence issued by T2 is not useful - T1 has issued the stores; the fence issued by T2 will complete any loads/stores issued by T2 up to that point. This will not cause visibility of the stores issued by T1.