Why 'make' always rebuilds the target?

My Makefile is:

OBJS = b.o c.o a.o
FLAGS = -Wall -Werror
CC = gcc

test: $(OBJS)
    $(CC) $(FLAGS) $(OBJS) -o test
b.o: b.c b.h
    $(CC) $(FLAGS) -c b.c
a.o: a.c b.h c.h
    $(CC) $(FLAGS) -c a.c
c.o: c.c c.h
    $(CC) $(FLAGS) -c c.c
clean:
    rm a
    rm *.o
all: test

If I do make then make again, it always rebuilds 'test'. Why does it do this?

Even if i do: make a.o it rebuilds... Im on linux if that helps.

In windows if I change 'test' by 'test.exe' and '-o test' by '-o test.exe', it works fine. So I guess that for some reason 'make' in my linux cant check the datestamps of my files in the directory.

I FIXED IT! The .c were created in Windows. I opened all .c and .h in vi, and without doing nothing save changes, and all work开发者_运维百科ed. I think that the datestamp thing was fixed doing this.

Your first rule is:

test: $(OBJS)

That means if a file named 'test' doesn't exist, the rule should run and create it. Since 'test' never exists (that rule doesn't actually create a file named 'test'), it runs every time. You should change 'test' to 'a', the actual output of that rule

For future reference, if a rule doesn't actually create the thing on the left-hand side, you should mark it with:

.PHONY: test

You need to specify that test is a phony target:

OBJS = b.o c.o a.o
CFLAGS = -Wall -Werror
CC = gcc

.PHONY: all test clean
# 'all' and 'clean' are also phony

all: test
test: a

a: $(OBJS)
    $(CC) $(CFLAGS) $(OBJS) -o a

b.o: b.c b.h
a.o: a.c b.h c.h
c.o: c.c c.h

clean:
    rm a
    rm *.o

I've placed all first so it is the default target (which is common), removed the commands for compiling (make already has those built-in), and changed FLAGS to CFLAGS (which is the common name for C compiler flags and used by make's built-in rules).

As a last resort you can run Make in debug mode (make -d) and comb through the output. Before trying that, I suggest you add a line to the "test" rule to see if there are any prerequisites that Make thinks require the rebuilding of test (and use some automatic variables in the compile command, as a good practice).

test: $(OBJS)
    @echo prereqs that are newer than test: $?
    $(CC) $(FLAGS) $^ -o $@