Is there any advice you have for programming efficient System Verilog code? [closed]

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I have been working on a project using System Verilog where one of the goals is to make the code more efficient. I have been using spare time to read different papers and books on how to program in System Verilog, but given people's experience using System Verilog, if there would be any advice on what to do, what to not do, what leads to a more efficient synthesized circuit etc. It would be nice to have more advice in a single place. Otherwise if there are any resources on writing efficient System Verilog code that would also be incredibly helpful. Thank you in advance.