MakeFiles and dependencies
I'm writing a makefile and I can't figure out how to include all my source files without having to write all source file I want to use. Here is the makefile I'm currently using:
GCC = $(GNUARM_HOME)\bin\arm-elf-gcc.exe
SOURCES=ShapeApp.cpp Square.cpp Circle.cpp Shape.cpp
OBJECTS=$(SO开发者_开发知识库URCES:.cpp=.o)
EXECUTABLE=hello
all: $(EXECUTABLE)
$(EXECUTABLE): $(OBJECTS)
#$(CC) $(LDFLAGS) $(OBJECTS) -o $@
.cpp.o:
$(GCC) -c $< -o $@
How do I automatically add new source file without having to add it to the sources line?
Here is something I have used in an examples/
directory where each file is mapped one-to-one to an executable:
sources := $(wildcard *.cpp)
programs := $(sources:.cpp=)
[ more settings about compiler flags, linker options, ...]
all : $(programs)
That can be enough as make
knows how to turn a .cpp file into an object file and then into an executable. Note that this is on Linux so for Windoze you'd probably need to do
programs := $(sources:.cpp=.exe)
to append the .exe.
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