Are you allowed to have a module identifier be the same as the module type in Verilog?

For example

module top
    debouncer debouncer(...);
endmodule

module debouncer
...
endmodule

Can I instantiate a debouncer as "debouncer" in the top m开发者_运维知识库odule, or is that illegal?

Yes, it is legal for a module instance name to match the module name in Verilog, and it is quite common to do so when you only need one instance of a module. But, you could have quickly verified that for yourself by simply compiling your file with your favorite simulator. The following is legal syntax and compiles for me:

module top;
    debouncer debouncer();
endmodule

module debouncer;
endmodule