Producing a clock glitch in a Verilog design

I am designing a chip using Verilog. I have a 3-bit counter. I want that when the开发者_Python百科 counter is in its 8th loop, there should be a clock glitch, and thereafter work normally. What could be the possible ways of producing a clock glitch in a Verilog design?

One way to inject glitches on a clock signal is to use force and release from your testbench:

module tb;

reg clk;
reg [2:0] cnt;
reg reset;

always begin
    #5 clk <= 0;
    #5 clk <= 1;
end

always @(posedge clk or posedge reset) begin
    if (reset) begin
        cnt <= 0;
    end else begin
        cnt <= cnt + 1;
    end
end

always begin: inject_clk_glitch
    wait(cnt == 7);
    #1 force clk = 1;
    #1 force clk = 0;
    #1 release clk;
end

initial begin
    reset = 1;
    #20 reset = 0;
    #500 $finish;
end

endmodule

So you essentially want an extra clock edge? I can't think of a way to do this in RTL. You may be able to do an ugly hack utilising gate delays, but this would need to be characterised over temperature and process variations.

I'd recommend that you think of another solution to your problem. Why do you need this extra clock edge?