wire equation in verilog [closed]

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If say I have the following wire set-ups, is the wire assignment all valid?

wire[3:1] w;
wire w1;
wire [1:0] w2;

A) w1 = w[2];    
B) w2 = w[1:0];  
C) w2 = w[1:2];

I am guessing that everything is valid....

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Don't guess. Try to compile the code for yourself. A and B are legal syntax. C is illegal syntax, according to the simulators I tried (VCS and NC-Verilog), assuming you mean:

assign w2 = w[1:2];

The compile error message will be something like "Illegal part select range".

In the IEEE Standard for Verilog (Std 1364-2005), section 5.2.1 "Vector bit-select and part-select addressing", it is stated that the 1st number must address a more significant bit than the 2nd number.