make - specifying target name to make from command line

I am looking at C makefile, and I have a question.

I know that 'make a' will make the target a, which is supposed to be defined in the makefile.

I want to know whether the target name itself can be supplied as an argument to make.

i.e. this is what I want to do:

$(target_name) is the name supplied to command 'make'. For example, 'make foo'.

and in the makefile,

$(target_name) = dependencies

command

I am not sure whether this is possible... could not find anything in the make 开发者_StackOverflowmanual too.

If anyone can help me with this, it'll be awesome.

Thanks,

Everything you are asking about is what make does by default - there is no need to write any special code in the makefile to do this. You seem rather confused about make (it is not particularly C related, for example). The best guide to it is the GNU Make Manual, which is not only a manual but a pretty good tutorial.

I'm kind of new to Makefiles but it seems you don't pass values in Makefile like that. If the following is your Makefile

# Makefile

TARGET?=something

$(TARGET):
    echo $(TARGET)

You can pass parameters in by calling make like this in the terminal

$ TARGET='ABCDEF' make