Is there any special significance of a parenthesis in Verilog when used to wrap a parameter?

I have a piece of Verilog code worked upon by a programmer no longer in the company I work for. An extract is given below:

parameter mstrobe = 10;
.
.
.
assign #(mstrobe) sclk=iclk;

(sclk is a wire, iclk is assigned the value of system clock)

I also have a separate Perl script for carrying out some manipulations on existing Verilog files. This script chokes in parsing #(mstrobe) because mstrobe is enclosed 开发者_Python百科within parenthesis. While I can fix that easily, what I want to know is whether there is a fundamental difference between the assign statement above and

assign #mstrobe sclk=iclk;

I want to be sure whether the two statements are equivalent, or perhaps whether there are any differences in syntax in this regard between Verilog versions (Verilog-2001, Verilog-2005, SystemVerilog).

In your simple case, the parentheses are optional; both cases are valid syntax, regardless of Verilog version.

The parentheses would be required if you had a more complex expression, such as:

assign #(mstrobe/2) sclk=iclk;

On a side note, since you are parsing Verilog using Perl, are you aware of Verilog-Perl?

The other time that parenthesis are used in that context is when the delay specifies the timestep. Your example will delay 10 (or whatever mstrobe is set to) timeunits determined by your timescale. You could however do #(10ps) where mstrobe = 10ps this would guarantee you delay 10ps independent of your timescale. I'm not sure if they are required when specifying timescale, but it is good coding practice.