Creating a makefile that recursively calls makefiles in subdirectories

I am trying to create a Makefile in the root directory that creates an output (/bin) directory and then recursively goes into subdirectories, looking for a Makefile, calling it with the files in that directory, and outputing everything in /bin.

The Makefile in the root is the following:

DIR=bin
OUT_DIR=/bin
MAKE=make
CURRENT_DIR=./Server
ROOT=.

all: compile

compile: dir
    export ROOT;
    export OUT_DIR;
    export CURRENT_DIR;
    export开发者_如何学JAVA;
    $(MAKE) -C $(CURRENT_DIR)

dir:
        mkdir -p $(DIR);

clean:
        rm -rf $(OUT_DIR)/*

The bin directory gets created, and it seems like the Makefile in the server directory also gets called (I don't have a loop to go into subdirectories yet).

In my Makefile in Server, where two .java files are, I have the following:

JC=javac

all: server

server:
    echo $(OUT_DIR);
    echo $(CURRENT_DIR);
    $(JC) -d $(OUT_DIR) $(CURRENT_DIR)/*.java

What is happening is when I call "export" in the initial Makefile, the variables I am trying to export are not exported and I do not understand why.

I would really appreciate if someone could please point me towards my question and also point me towards an elegant solution to solve my overall problem please.

Makefiles are a bit tricky for me at this point: There seem to be multiple ways to achieve a similar solution, and I am not sure which one is more appropriate and elegant.

Your exports are on multiple lines and therefore in different shell invocations. Put a \ at the end of a line to join them.

It is a little more elegant at this point to export the variables directly in the Makefile, e.g. state

ROOT=.
export ROOT

It is even more elegant to use automake and have it generate the makefile for you.

It is even even more elegant to use non-recursive makefiles.