How can I output a value to a register with a Verilog task?

My understanding of Verilog tasks is that they act like subroutines and are able to accept both input and output parameters. Using $display, I can peek at the values of my register variables along the way. For some reason my output register does not seem to overwrite the argument. Here is an example:

`timescale 1 ps / 1 ps
`default_nettype none

module testbench;
reg clk;
reg data_reg = 8'h00;

always begin // 100MHz clock
    clk = 1'b1;
    #(5000);
    clk = 1'b0;
    #(5000);
end

task copy(input reg [7:0] din, output reg [7:0] dout);
begin
    $display("copy: before: din=%h, dout=%h",din,dout);
    @(negedge clk);
    dout = din;
    @(negedge clk);
    $display("copy: after: din=%h, dout=%h",din,dout);
end
endtask

initial
begin
    $display("data_开发者_StackOverflow社区reg=%h",data_reg);
    copy(8'hBC, data_reg);
    $display("data_reg=%h",data_reg);
    copy(8'h00, data_reg);
    $display("data_reg=%h",data_reg);
    $display("done");
    $finish;
end

endmodule

And here is the output of the icarus-verilog simulator:

data_reg=0
copy: before: din=bc, dout=xx
copy: after: din=bc, dout=bc
data_reg=0
copy: before: din=00, dout=bc
copy: after: din=00, dout=00
data_reg=0
done

Why doesn't the register data_reg get overwritten when the copy task is called?

You forgot to set the width for reg data_reg so it is 1 bit wide and you happen to be assigning an even value to it so it is zero.