Why is my mux not producing an output in Verilog?

I've written what I thought would be a working MUX, but my output is stubbornly staying at high-impedance. Can someone please provide me with guidance?

module mux_in #(parameter WIDTH = 1, parameter LOG_CHOICES = 1)
(
    input  [LOG_CHOICES - 1 : 0] choice,
    input  [(1 << LOG_CHOICES) * WIDTH - 1 : 0] data_i,
    out开发者_高级运维put [WIDTH - 1 : 0] data_o
);
    assign data_o = data_i[WIDTH * choice + WIDTH - 1 : WIDTH * choice];
endmodule

Here's my (bad) output:

data_i: 11111010101111100001001100100010
data_o: zzzzzzzz
Choice 0: (Expected  34) Output:   z
Choice 1: (Expected  19) Output:   z
Choice 2: (Expected 190) Output:   z
Choice 3: (Expected 250) Output:   z

This should not compile because the range expression is not constant.

assign data_o = data_i[WIDTH * choice + WIDTH - 1 : WIDTH * choice];

Try this instead.

assign data_o = data_i[WIDTH * choice + WIDTH - 1 -: WIDTH];