Converting a wire value in Verilog for further processing

I'm new to Verilog.

I have written code to conve开发者_JS百科rt a wire value to an integer:

wire [31:0] w1;
integer k;
always @ (w1) k = w1;

Source: converting a wire value to an integer in verilog

Now, for the next part I get an ERROR!

wire [63:0] w2; // Suppose it contains some value
wire [63:0] w3;
assign w3[k-1:0] = w2[k-1:0]; // ERROR in this line

ERROR : k is not a constant.

How do I solve this issue?

Verilog requires that part selects (code like [msb:lsb] to select part of a vector) be constant. To access a variable-sized group of bits requires something more complicated. Here is one way to do it:

wire [63:0] src;
wire [6:0] k;

wire [127:0] mask = { { 64 { 1'b0 } }, { 64 { 1'b1 } } } << k;

wire [63:0] dest;

assign dest = mask[127:64] & src;

The technique here is to construct a vector of 64 zeros followed by 64 ones, shift that vector by a variable amount, and then use a portion of the vector as a qualifying mask to control which bits are transferred from src to dest.

A related concept which does not help in your example but which is worth being aware of: Verilog-2001 introduced the "indexed part-select". An indexed part select specifies a base index and a width. The width is required to be constant but the base index does not need to be constant. The syntax for an indexed part select is vec[base+:width] or vec[base-:width].

The part select operators in Verilog 2001 could be useful for what you want to achieve.

Basically verilog allows for the starting index to be variable but needs the width of the assignment to be constant. The "+:" operator indicates counting upwards from the index value and vice-versa for "-:".

You can do something like, assign w3[k-1 -: 8 ] = w2[k-1 -: 8]; // Where 8 bits is copied downwards

Search for "+:" in the below document. http://www.sutherland-hdl.com/papers/2001-Wescon-tutorial_using_Verilog-2001_part1.pdf

Word of caution, generally variable part selects is considered as bad verilog.