Makefile target matching

I'm having troubles with my Makefile :-(

I have a mix of assembly and C sourcecode that I need to link together. I need different build-instructions for those two types. Since 开发者_如何学运维both the assembler and C compiler output *.o files, I cannot use the general %.o:%.c construction often found in example Makefiles

This what I'm trying now:

Get a list of all C files and their resulting output files:

C_SRCFILES := $(shell find $(SRCDIRS) -type -f -name "*.c")
C_OBJFILES := $(patsub %.c,%.o,$(C_SRCFILES))

Get a list of all asm files and their resulting output files:

A_SRCFILES := $(shell find $(SRCDIRS) -type -f -name "*.asm")
A_OBJFILES := $(patsub %.asm,%.o,$(A_SRCFILES))

When I echo those vars to the screen, they seem to be correct, but how I do define my targets now?

I tried something like this

$(A_OBJFILES): ($A_SRCFILES)
  $(AS) $(AFLAGS) -o $@  $*

$(C_OBJFILES): ($C_SRCFILES)
  $(CC) $(CFLAGS) -c -o $@ $*

all: $(A_OBJFILES) $(C_OBJFILES)
  $(LD) $(LDFLAGS) $(A_OBJFILES) $(C_OBJFILES) -o $(TARGET_OUTPUT)

but ofcourse, this doesn't work...

Any suggestions?

First problem: a misplaced parenthesis or two.

$(A_OBJFILES): ($A_SRCFILES)

Notice that you have the $ inside the ( in ($A_SRCFILES). Make expands $A, which is nothing, and things go downhill. I think you meant $(A_SRCFILES), and the same thing in the other rule.

Second problem: I don't know the syntax of the assembler, but the syntax of the compiler command is wrong:

$(CC) $(CFLAGS) -c -o $@ $*

The variable $* is nothing if we're not in a pattern rule, which we're not (yet). And anyway, if we were in a pattern rule and you were trying to build foo.o, this command would look for the source file foo, and there's no such file. Do it this way:

$(CC) $(CFLAGS) -c -o $@ $<

Third problem: each object file depends on all source files (in each rule). Try this instead:

$(A_OBJFILES): %.o : %.asm
    ...

$(C_OBJFILES): %.o : %.c
    ...

(Now it's a pattern rule.)

Fourth problem: a lot of redundancy in the last rule. Change it to this:

all: $(A_OBJFILES) $(C_OBJFILES)
    $(LD) $(LDFLAGS) $^ -o $(TARGET_OUTPUT)

or better still:

all: $(TARGET_OUTPUT)

$(TARGET_OUTPUT): $(A_OBJFILES) $(C_OBJFILES)
    $(LD) $(LDFLAGS) $^ -o $@

Since both the assembler and C compiler output *.o files, I cannot use the general %.o:%.c construction often found in example Makefiles

Sure you can:

%.o : %.c
    # commands to make .o from a corresponding .c

%.o : %.asm
    # commands to make .o from a corresponding .asm