Calling an external shell script inside a makefile for setting variables

Take a look at the following makefile (which isn't working) ...

export CC      = gcc
export CFLAGS  = -W -Wa开发者_开发知识库ll -fPIC -m32

USER = $(DB_USER)
export USER

PASS = $(DB_PASS)
export PASS

SUBDIRS = libs dbserver

.PHONY: subdirs $(SUBDIRS)

subdirs: $(SUBDIRS)

$(SUBDIRS):
    $(MAKE) -C $@

The variables DB_USER and DB_PASS are defined in a separate external file, conf.sh, like this:

export DB_USER=<username>
export DB_PASS=<password>

These are then required in makefiles inside SUBDIRS.

If I run . conf.sh on the command line, and then call make, then USER and PASS are assigned the correct values, and compilation is done all fine. But I wish to call conf.sh inside the makefile so that these variables can be set. How can I accomplish this?

You could use:

$(SUBDIRS):
    . conf.sh; $(MAKE) -C $@ DB_USER="$${DB_USER}" DB_PASS="$${DB_PASS}"

This will expose the password on the command line, but gets the job done. Note the double-dollars; that part is evaluated by the shell, not by make (so the curly brackets are also necessary). I'm not sure I recommend it, but it should work.

Come to think of it, you could probably avoid passing the parameters explicitly since the conf.sh script exports them. The values for $DB_USER and $DB_PASS will be available to the subordinate make anyway:

$(SUBDIRS):
    . conf.sh; $(MAKE) -C $@

EXPORT defines a variable in the current shell. The variables are not visible in the caller.