How do I avoid these repetitions when using recursive make?
Suppose I开发者_JAVA技巧 have a project with two or more subfolders foo
, bar
, etc. I have a Makefile
at the root of the project, and also in each subdirectory.
I would like to have certain targets (e.g. all
, clean
, etc) to run recursively in each subdirectory. My top-level Makefile
looks like this:
all:
$(MAKE) -C foo all
$(MAKE) -C bar all
clean:
$(MAKE) -C foo clean
$(MAKE) -C bar clean
Seems to me there's a lot of duplication going on here. Is there a way I can avoid such tedious duplication in my Makefiles?
How about this:
SUBDIRS=foo bar
all clean:
for dir in $(SUBDIRS) ; do \
$(MAKE) -C $$dir $@ ; \
done
A bit scary:
SUBDIRS=foo bar
SUBDIR_TARGETS=all clean
define subdir_rule
$(2): $(1)-$(2)
$(1)-$(2):
make -C $(1) $(2)
endef
$(foreach targ,$(SUBDIR_TARGETS),\
$(foreach dir,$(SUBDIRS),\
$(eval $(call subdir_rule,$(dir),$(targ)))))
Here's how I'd do it:
SUBDIRS=foo bar baz
TARGETS = clean all whatever
.PHONY:$(TARGETS)
# There really should be a way to do this as "$(TARGETS):%:TARG=%" or something...
all: TARG=all
clean: TARG=clean
whatever: TARG=whatever
$(TARGETS): $(SUBDIRS)
@echo $@ done
.PHONY: $(SUBDIRS)
$(SUBDIRS):
@$(MAKE) -s -C $@ $(TARG)
精彩评论