Is the 2D array synthesizable in verilog

The memory is always 1D so does the 2D or 3D array which works fine in simulation gets synthesized in verilo开发者_开发技巧g?(the word size is 8 bit)

It depends on the synthesis tool and what you are trying to do. It is supported to be able to infer RAM structures from a 2D array with all of the synthesizers I have used before. Doing anything more exotic is probably not supported. A module with a 2D array like this will be synthesized.

    reg [DATA_WIDTH-1:0]     mem [0:DEPTH-1]; // memory array.

    always @(posedge clk)
      if (we) mem[addr]