Why can't I instantiate inside the procedural block in Verilog

I need to instantiate some modules whose requirements pop u开发者_运维百科p during the procedural block.But I am not allowed to instantiate inside the procedural block.Where else should I instantiate these modules so that I could access them in the procedural block.

I just need 1 instantiation and so I am not using generate statement.I am simply instantiating it using ...Center data_cent(.clk(clk),.dummy_4(dummy_6));

But upon checking the syntax it gives an error stating " data_cent is not a task". I am unable to figure out the problem. I would be glad if some one could help.

You can instantiate it inside a module, but outside of any procedural blocks. If you want to access internal nets of your subinstance, you can use hierarchical specifiers. For example, if your instance contains an internal net named foo:

module top;

Center data_cent(.clk(clk),.dummy_4(dummy_6));

initial begin
   $display(data_cent.foo);
end

endmodule

SystemVerilog also offers the bind construct.

From your description, I can think of two possibilities:

1. You may be writing a generic code and you need to instantiate according to the parameter values. If this is the case, you can use generate if.
2. You may want to instantiate according to a signal value during run time. In this case you are thinking as a programmer not as a hardware designer. Instantiating means adding hardware and you can't make a signal value decide whether the hardware exists or not. The hardware is just there or not there - no third choice except for FPGA and it is not that simple.
   I think what you need is to instantiate the module outside always and make enable signal that you can modify inside always to make the module work when the condition is met.