Makefile - loop through a list and select a specific value

I'm trying to do something like this (assuming $input is something provided by the user):

LIST = pre1 pre2 pre3 pre4 pre5 pre6 pre7 pre8 pre9 pre10
START = 0

for prefix in $(LIST); do \
    if $(input) == $(prefix) then
        START = 1
    endif \
    if $(START) == 1 then \
        if [ -f  $(prefix)<file_name> ]; then <do_A>; else <do_B>; fi
    endif \
done

my problem is with th开发者_JAVA百科e two if's mentioned above. i don't know how can i choose a specific string value from a list while iterating it (if $(input) == $(prefix) then) and i don't know how to check if a value is 1 or 0 (if $(START) == 1 then).

My intent with this code is to use the same makefile for different directories which have the same file name, but with a different prefix. sometimes, a directory might contain multiple versions of the file with a different prefix and i want to define a hierarchy of those prefixes (defined by LIST in my example). when the user provide a version, the idea is to start searching for the most up-to date version, starting from the version he provides (e.g. if the user provide pre4, then i need to search pre4 first and if it's not exist - i'll go on and search for pre5 and so on. but in this example, i won't search for pre1 even if it do exist in the current directory).

Anyone has an idea on how can i do that?

Thanks in advance.

If that is supposed to be a command in a Makefile, the syntax would have to be something like this:

LIST = pre1 pre2 pre3 pre4 pre5 pre6 pre7 pre8 pre9 pre10
START = 0
input = somename
file_name = whatever

some_target:
    for prefix in $(LIST); do \
        if test "$(input)" = $$prefix; then \
            START=1; \
        fi; \
        if test "$(START)" = 1; then \
            if test -f  $$prefix$(file_name); then \
                <do_A>; \
            else \
                <do_B>; \
            fi; \
        fi; \
    done

But you didn't tell us what <input> and <file_name> are supposed to be, so I assumed they are other make variables. Basically the make rules look like one long shell line, with commands separated by semicolons, and lines continued with backslashes. $$ is replaced by make with a single $, which is why references to shell variables ($$prefix) need two dollars.

Your make manual (type man make has the whole story and is fun to read and understand.) Become a make guru today! Be sure to understand the difference between a make variable and a shell variable.