How can I manage make targets that don't have suffixes?

I've got a make file that generates multiple targets. Something like:

target-a: target-a.src target-include.src
        @$(BUILD_TOOL) -f $< -o $@
target-b: target-b.src target-include.src
        @$(BUILD_TOOL) -f $< -o $@
target-c: target-c.src target-include.src
        @$(BUILD_TOOL) -f $< -o $@

The actual build process (abbreviated as $(BUILD_TOOL) above) is a multiple line thing involving compilers, scripts and various whatnot, but suffice to say, the build process acts on the first target dependency ($<) and produces the output target ($@).

This is quite unwieldly. Would what I've got below be considered a safe way to replace the above (using a pattern rule that doesn't have a suffix)?

all: target-a target-b target-c

% : %.src target-include.src
        @$(BUILD_TOOL) -f $< -o $开发者_如何学Python@

The make tool is GNU, and I'm content to use it's powerful extensions.

If target is a literal string, renierpost's solution is very good. If it isn't (or even if it is) this will work:

TARGETS := target-a target-b target-c

all: $(TARGETS)

$(TARGETS): % : %.src target-include.src
    @$(BUILD_TOOL) -f $< -o $@

Note that this rule will not build targets you did not intend, not even target-include.

It depends on the rest of your Makefile, but in principle this should work, if all files are in one directory.

It's better practice to use extensions on your targets.

Is target a literal string? In that case, you can be more specific (and speed up rule application a tiny little bit, but it's fast already) by using

all: target-a target-b target-c

target-% : target-%.src target-include.src
    @$(BUILD_TOOL) -f $< -o $@

GNU make's advanced syntax will come into play if you want to automatically deduce the names of target-a target-b target-c from the target-*.src filenames on the filesystem or something similar.