Makefile with macro, does not generate any executable

I wrote a Makefile(code below) for my program which contains hello.h, hello.cpp and main.cpp (this is a trivial testbench for hello.cpp).

However, after I type make in the terminal, it tells me

make: `hello.o' is up to date.

Can someone give any hints? Thank you!

#MACRO
CAT_HOME = $(MGC_HOME)
TARGET = my_tb
#OBJECT1 = hello.o
OBJECTS = hello.o main.o
#OBJECT2 = main.o
DEPENDS = hello.cpp main.cpp hello.h
INCLUDES = -I"$(CAT_HOME)/shared/include"
DEFINES =
CXX = /usr/bin/g++
CXXFLAGS = -g -O3 $(DEFINES) $(INCLUDES)

$(TARGETS) : $(OBJECTS)
    $(CXX) $(CXXFLAGS) -o $(TARGET) $(OBJECTS)

$(OBJECTS) : $(DEPENDS)

#phony target to remo开发者_如何学Pythonve all objects and executables
.PHONY: clean
clean:
    rm -f *.o

You define a TARGET variable but later try to use $(TARGETS). Theres an S in difference.

Also, it is inefficient to let every .o file depend on every .cpp file. You might as well just write a linear script that recompiles everything unconditionally. Since you're depending on make's built-in rule for creating a .o from the corresponding .cpp, you don't need to declare that dependency explicitly. So you can remove all of the .cpp files from DEPENDS without losing any relevant dependencies.