How do you run a command prior to including a component Makefile?

I am trying to create a subdirectory in my project (let's call it $PROJECT/child) that needs to pull in a Makefile (let's call it ../Makefile.inc) from its parent, $PROJECT/Makefile.inc. Later I want to c开发者_Go百科opy $PROJECT/child somewhere else so it can run independently of $PROJECT.

There is a common Makefile that needs to be included in both projects and shipped when the subdirectory is copied, and I want it to be included in both cases. So I thought I would link it in during the child build, if it isn't found. (I don't want to just include ../Makefile.inc, because this will disappear when I copy the project, and I don't want the calling build system to be responsible for putting the Makefile.inc in place.)

With those constraints, here's a horrible hack that I've come up with to do this, within $PROJECT/child/Makefile:

HACK = $(shell test -f Makefile.inc || ln -f  ../Makefile.inc .)
include $(HACK)Makefile.inc

Notice the extra special duct tape on that second command. I have to actually include $(HACK) even though it's going to end up empty, so that the $(shell ...) will be evaluated. ;-)

Is there a cleaner way to make this happen?

Give a rule to build Makefile.inc. (make will complain that Makefile.inc doesn't exist when it parses the include line, but it will go on parsing the main makefile, apply any rule to build included files, and go back and re-parse the main makefile with the included files.)

include Makefile.inc
Makefile.inc:
        ln ../Makefile.inc $@