Variable substitution error

Does anyone know what is wrong with my Makefile?

CXX = g++               # compiler
CXXFLAGS = -g -Wall -MMD        # compiler flags
MAKEFILE_NAME = ${firstword ${MAKEFILE_LIST}} # makefile name

OBJECTS1 = utf.o            # object files forming executable
EXEC1 = utf             # executable name

OBJECTS2 = driver.o rational.o # object files forming executable
EXEC2 = rational            # executable name

OBJECTS3 = da.o qa.o pa.o ua.o # object files forming executable
EXEC3 = ho          # executable name

OBJECTS = ${OBJECTS1} ${OBJECTS2} ${OBJECTS3}
EXECS = ${EXEC1} ${EXEC2} ${EXEC3}
DEPENDS = ${OBJECTS:.o=.d}      # substitute ".o" with ".d"

.PHONY : all clean

all : ${EXECS}

${EXEC1} : ${OBJECTS1}          # link step
    ${CXX} $^ -o $@

${EXEC2} : ${OBJECTS2}          # link step
    ${CXX} $^ -o $@

${EXEC3} : ${OBJECTS3}          # link step
    ${CXX} $^ -o $@

${OBJECTS} : ${MAKEFILE_NAME}       # OPTIONAL : changes to this file => recompile

-include ${DEPENDS}         # include *.d files containing program dependences

clean :          开发者_StackOverflow社区       # remove files that can be regenerated
    rm -f ${DEPENDS} ${OBJECTS} ${EXECS}

Error:

./Makefile: 1: CXX: not found
./Makefile: 2: CXXFLAGS: not found
./Makefile: 3: Bad substitution

use the make command to run the Makefile. you can specify a target for make, like make all.

Don't execute the makefile on its own. Your shell is trying to treat it as a shell script of some kind.

Run make, which uses the makefile.