Can caches have limitations when dealing with devices?

In my computer architecture class, the prof posed the following que开发者_如何转开发stion to us:

"Caches can have serious limitations when dealing with devices. Why is this?"

I have no idea why there are limitations or what they could be. After a search on Google, I can't seem to find an accurate answer to this. Can someone explain why there are limitations and what those limitations may be, or point me in a direction that may help me in answering the question?

In other words, you have no control on what/when is actually sent to device.

There are two problems with cache and devices. The first problem is one of basic functional correctness. Namely, the system must generally place the device's memory-mapped registers in an address range that bypasses the cache entirely. Imagine this did not happen and cache was "in the way". In that case, software trying to read a status register on the device would read instead the stale value provided by the cache! Good luck getting your device drivers to work. Some CPUs provide special instructions for uncacheable accesses, but the basic result is same, in that cache offers no benefit and only complicates matters when dealing with device memory.

The second problem is a performance issue with smart devices capable of doing direct memory access (DMA) transactions with memory. When a device performs a DMA write then hardware bus logic in the system snoops the cache lines completely away from the CPU following the MESI protocol. Cores depend strongly on keeping data in close caches for efficiency. Now, the device has just yanked all the cache lines away, which forces the core into a high latency reload of the lines on the next software access. The same snooping usually happens even for DMA reads since CPU's often avoid data lines the shared state.

Devices integrated into the CPU itself may be able to leave the cache lines resident in the CPU's last level cache, which can be a significant performance boost vs. devices outside the CPU package.

Basically you have to have a way to know exactly when data is flushed out of cache and into the device you're talking to. RAM is a device like any other and it remembers the last data that was written to a location. If it wouldn't be stored in RAM, then a device also wont see the write. Linux uses functions called read/write barriers that are architecture dependent.

How Linux deals with it