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Assembly replace CMP by EORS before a jump

I'm using an ARM processor, but 开发者_StackOverflowI assume the question is the same for all processor.

I'd like to use an EOR instruction (bitwise exclusive OR) instead of a CMP because I must find the unmatching bits after the jump.

But, I don't know why it seem's that

CMP r0, r1
BNE .somewhere

is not "equivalent" to

EORS r5, r0, r1
BNE .somewhere

Is it normal or must I look for my problem again ?

Thank's


CMP is not "equivalent" to EORS. A CMP instruction is basically a SUBS that throws away the result of the subtraction.

There is an ARM instruction that does an EORS but throws away the result. It is TEQ. Perhaps you wanted that instead of CMP?


CMP subtracts r1 from r0 (r0-r1) and then sets a flag for the BNE as to whether or not the two are equal (the result is 0) or not equal (the result is not 0).

In order to subtract in binary, you would use "twos compliment", where you take r1, negate it, add 1 to it and then add that to r0. If the result of the addition is all 0s it flags to equal. Otherwise it flags as unequal. The most important thing to remember here is that there is a flag. In this case, it sets the "Z" flag. Thus BNE can operate correctly.

r0 (00100000) [32]

r1 (00111000) [56]

Negation of r1: (11000111) [-57] #The first bit of a signed number indicates whether it is negative usually. 1 usually means negative when in front like that. Adding the values: # Remember it's basically a standard OR operation but with a carry function if both bits are 1.

(00100000)

(11000111)

ADD

(11100111) # This is not 0 and therefore does not set the Z flag.

EOR does a logical bitwise operation on the data in r0 and r1 by XORing them together and then storing the result in r5.

It does this like so: XOR results in a 0 if both bits are 0 or both bits are 1. Otherwise it yields a 1.

r5 (00000000) # For simplicity, I'm going to assume r5 is empty.

r0 (00001111)

r1 (00011111)

XOR (00010000)

r5 (00010000) # The XOR result copied to r5.

You used the S suffix which does trigger the flag so that solves it, right?

What is the other difference beyond the operations? The destination registers. I suspect that you'd need to store in r0 rather than r5 since BNE may not be checking r5. That's my take on it anyway.

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