Can a TLB hit lead to page fault in memory?

In UC Berkley Video lectures on OS by John Kubiatowicz (Prof. Kuby) available on web, he mentioned that TLB hit doesn't mean that corresponding page is in main memory. Page fault can still occur.

Technically TLBs are cache for page table entry and since all page table entries don't have their corresponding 开发者_运维问答page available in main memory. Same can be true for TLBs. A TLB hit may lead to page fault.

But according to algorithms given in text books I am unable to find such a case. On a TLB miss kernel refer to page tables and update the TLB cache for appropriate address translation. Next TLB hit can't lead to page fault. When kernel swap out the page, it updates the appropriate bits for that page table entry and invalidate the corresponding TLB, so there can't be a TLB hit next time until page is loaded in main memory.

So can someone stand for correctness of Prof kuby's claim and point out a case when instead of TLB hit (the translated physical address for corresponding virtual address in found in TLB), a page fault can occur?

One example is if the memory access is different from the allowed one.

e.g. you want to write to memory that's write protected. A TLB exists, it's a hit and the address is translated. But on access you get a trap, as you're trying to write to memory that's read-only

A page fault doesnt mean a missing page in the memory. A page can still be present and be dirty. This is also a page fault. On a general note, the page fault refers to the scenario where the obtained translation cannot be effectively used. It may be a missing page or a dirty page or access permission mismatch. So a TLB hit can still lead to a page fault.

patterson says:"cannot have a translation in TLB if page is not present in memory" [computer organization and design,4th ed revised, page 507]