makefile macro taking arguments

I'd like to make something of my own like the shell macro where you can say $(shell command).

Unfortunately, I haven't found anything online about how to do this.

Is that po开发者_StackOverflow中文版ssible?

In GNU make you can do something like the following. Imagine you want to generate the .h and .cpp file names from a simple file name without extension to be added as a sources of some rule. You can write:

define h_and_cpp_sources
    $(1).h $(1).cpp
endef

This generates a Makefile macro that gets the first parameter as $(1), second as $(2), and so on. Then:

target: $(call h_and_cpp_sources,file)
...

This will construct the rule:

target: file.h file.cpp

You should try with the call function syntax.

It's not exactly what you want, but AFAIK there is nothing more elaborate than that.