Verilog, comparison to not equal bit of variable

I wonder if there is a poss开发者_运维问答ible way to comparison below variables.

reg [7:0] var1;
reg [3:0] var2;

Here I want to check if var2 is equal to last 4 bits of var1. Can I do that? If yes, how?

Like so:

if (var1[3:0] == var2)
    ...

Keep in mind that the reg type is for 4-state variables (01xz).

Either of these is appropriate for synthesizable RTL:

if (var1[3:0] == var2[3:0])
if (var1[3:0] == var2)

In a testbench it is better to use "triple equals":

if (var1[3:0] === var2[3:0])

You can do {if ~((var[3:0] ^ var2) | 4b'0000)}

This should be easier for the compiler to synthesize.