How to use const in verilog

Instead of using

module ... ( .. 开发者_高级运维)  ;

     #15 
endmodule

I want use

module ... ( ... ) ;
 // GateDelay is a const, like in c language const int GateDelay = 15 ;
 # GateDelay     

endmodule

Or same thing

module ... ( ... ) ;
 // assume Wordsize is defined at " define Wordsize 15 "
 reg [ Wordsize -1 : 0 ] mem ;

endmodule

Can I do that wish in verilog ?

You've a few options :

• Macros with `defines
• parameters
• localparams

Here's a small example with them all.

`define CONSTANT_MACRO 1          /* important: no ';' here */
module mymodule
    #( parameter WIDTH = 5 )
    ( 
      input wire [WIDTH-1:0] in_a,
      output wire [WIDTH-1:0] out_a
    );

    localparam CONSTANT_LOCAL = 2;

    assign out_a = in_a + `CONSTANT_MACRO - CONSTANT_LOCAL;

endmodule 

For the cases you listed, I would recommend parameters.

Like the C compiler directive, `define is global for the compilation. If your code is ever going to be used with code you don't control you will need to be careful here.

Parameters are always local to the module scope so identically named parameters in different design elements will not conflict with each other. They also have the advantage that they can be overridden on a per-instance basis.

module #(parameter DATA_WIDTH = 1) busSlave(
  input [DATA_WIDTH-1:0] bus_data,
  input                  bus_wr,
  ...
);

endmodule


module top;

  //DATA_WIDTH is 32 in this instance
  busSlave #(.DATA_WIDTH(32)) slave32(
    .bus_data(data_0),
    .bus_wr(wr_0),
    ...
    );

  //DATA_WIDTH is 64 in this instance
  busSlave #(.DATA_WIDTH(64)) slave64(
    .bus_data(data_1),
    .bus_wr(wr_1),
    ...
    );


endmodule