Loop unrolling and data cache performance

Does loop unrolling effect data cache performance in any way? This is related to a homework I have which requires me to simulate code on simplescalar sim-cache to test the effect of loop tiling, memory access in inner loop etc. on开发者_运维知识库 cache accesses and cache miss rate. The assignment specifically asks us to do loop unrolling but I do not understand how it can effect the data cache?

Loop unrolling in general will not affect L1 data cache, just the instruction cache. Since those two are different in most architectures. However if you have multi level cache architecture, Level 2 cache in most architectures serves as Level 2 cache for both instruction cache and data cache. Thus if you will unroll way too many instructions you might have effect on L2 cache, thus essentially descreasing performance of L2 as a data cache.

Here is picture of core i7 architecture which has separate icache and dcache but L2 cache is same for both. http://upload.wikimedia.org/wikipedia/commons/6/64/Intel_Nehalem_arch.svg