Setting target variable for the name of the makefile from a subdirectory

How can I have the variable for $(MAKEFILE) be defined during target execution? Basically I have a few make files in subdirectories that are named for a specific platform "Makefile.aix" and just Makefile in all other directories. I would like to set a variable for $(MAKEFILE) that gets defined in each subdirectory. Code would look something like this.

MAKEFILE = Makefile

SUBDIR = ./sub ./sub2

    ifneq ($(wildcard Makefile),)
            MAKEFILE = Mak开发者_JAVA百科efile
    else
            MAKEFILE = Makefile.$(PLATFORM)
    endif


    all:;
            @for i in $(SUBDIR);\
                    do (\
                            echo Making $$i ...;\
                            cd $$i;\
                            make -f $(MAKEFILE)\
                    ); done

Is there just one Makefile.$(PLATFORM) in each subdirectory, or are there several, for different platforms?
In the first case, you could do something like this:

SUBDIR = ./sub ./sub2

define script
cd $(1); \
$(MAKE) -f Makefile*

endef

all:
    $(foreach dir, $(SUBDIR), $(call script,$(dir)))

(The empty line inside the define is significant. It can be omitted, if you add a semicolon at the end of the line $(MAKE) ..., leading to one long command line, containing the commands for all directories, which will then be executed in one chunk.)

An alternative script would be (just a matter of personal preference which you like better):

define script
$(MAKE) -C $(1) -f $(notdir $(wildcard $(1)/Makefile*))

endef

If there are several Makefile.$(PLATFORM) files in a directory it becomes more difficult. I'll have to think about that one some more.

UPDATE: In response to your comment, something like this should work:

define script
$(MAKE) -C $(1) -f $(notdir $(wildcard $(1)/Makefile $(1)/Makefile.$(PLATFORM)))

endef

Following your logic, I'd propose update do () section with:

                do (\
                        echo Making $$i ...;\
                        cd $$i;\
                        if [ -f Makefile.$(PLATFORM) ] \
                        then\
                          make -f Makefile.$(PLATFORM) \
                        else\
                          make -f Makefile\
                        fi\
                ); done

This is actually not a make style, but I can't suggest anything better without specific of your project

You can do most of this, including the loop over directories, using GNU make's built-in functions. Put the following in a central place, say $(TOP_DIR)/mk/subdir.mk:

makefile-for-dir = \
  $(if $(wildcard $(1)/Makefile),Makefile,Makefile.$(PLATFORM))

make-recursive = \
  $(foreach _d,$(1),$(MAKE) -C $(_d) -f $(call makefile-for-dir,$(_d)) && ) :

In each makefile that start recursive makes, use

include $(TOP_DIR)/mk/subdir.mk

SUBDIRS = dir1 dir2 dir3

.PHONY: all
all:
    +@$(call make-recursive,$(SUBDIRS))