Is it possible to increment/initialize a variable inside 'generate' in verilog?

I have a doubt in the generate, my code is:

parameter m=1;

generate 
 for(i=0; i<m; i=i+1) :loopstart
 begin
  statements;
 end
endgene开发者_开发问答rate

Inside this loop, m should be 2^0, 2^1, 2^2, and so on. Since exponentiation is not supported, I thought of initializing m and then multiplying it by 2 on each iteration.

I have a few questions:

Is it possible to use m << 1 inside the generate in some way (since this is the same as multiplying by 2)? If I do that, it results in an error.

I referred to Samir Palnitkar's book, which says that always statement works inside a generate, so I tried:

always @(m)
 m <= m*2; // (or m << 1)

This doesn't work. I realize it can't be done because m is a parameter and not a variable.

If what I think is right, it can't be done with genvar either, since a genvar can't be initialized.

Is there an alternative?

The question seem to have been created because exponentials are not supported. They are :

2**0 => 1
2**1 => 2
2**2 => 4

NB:

always @(m)
 m <= m*2; // (or m << 1)

This is wrong for a few reasons

1. Do not use <= in combinatorial blocks
2. In the above expression m defines itself and re-triggers the loop.

I would also avoid named sensitivity lists and use always @* to avoid hardware simulation mismatches from incomplete sensitivity lists.

parameters and localparams are for defining constants, if they are not constant use something else like a logic or integer type.

logic [31:0] m = 0;
logic [31:0] power_two_m;
always @* begin
  power_two_m = 2**m;
  power_two_m = 1 << m;
end

Instead i++ use i=i+1

And.. forget C.