Make a Verilog module sensitive to a switch turning off

This would make a Verilog module sensitive to a clock and a reset switch being turned on:

always @(posedge clk, posedge rst)

How would this be changed to being sensitive to a switch being turn开发者_StackOverflow社区ed off?

If you want your block to be sensitive to a switch being turned off, you'll want a negedge in front of the name of the switch input, for example, "switch_line":

always @(posedge clock, posedge reset, negedge swtich_line)

If you just want to have a flipflop check the status of a switch on every positive edge of the clock cycle,

always @(posedge clock, posedge reset)
  if (!switch_line)
     // ...
  else 
     // ...

Are you trying to model a flip-flop, latch, or perhaps some new type of hardware? Usually, only flipflops and latches are interested in the clock signal. A flip-flop with an asynchronous reset is modeled as

 always @(posedge clock, posedge reset)

For a synchronous reset, drop the reset signal from the sensitivity list.

As per the user's comment, another option is to just plug-in the go signal for the reset signal. When you are hooking up this module, you can do the following:

mymodule UUT(
  .clock(clock),
  .reset(~go),
  //...
);

If you negate go, you'll get the same as behavior as reset, just inverted (e.g. a signal going from 1->0).

Unless you are running at a very low clock frequency the change in button state will be much slower that a clock period. Treating the button input as a async signal is therefore not a good idea. Instead you probably want to sample the input and also probably remove glitches.

As minimum sample the input by a register and then have your control FSM look at that register and when the expected change is detected move to the appropriate state. This means that it will take the design 1-2 cycles to "react" to the button change. But, again, unless the clock frequency is very low, the period will be short enough that no human will notice a few cycles latency.

If you connect the signal to the reset you (1) loose all state info by pressing the button (bad) and suddenly have two reset signals. Hot rodding the design like that might work, but is bad design methodology and will make your design sensitive to noise etc.