How to compile with a Makefile in sub-directories?

For a school project I need to create a Makefile that compiles sub-directories without using any other Makefiles. What I mean is that I am not allowed to do this:

make -C <sub-folder>

Here is how it looks like:

In local:

   ./Makefile
   ./sub
   ./sub2

And in sub directory:

   ./sub/file1.c
   ./sub/file2.c
   ./sub/file3.c
   ./sub/file4.c

   ./sub2/file1.c
   ./sub2/file2.c
   ./sub2/file3.c
   ./sub2/file4.c

Here is what I've done so far, but I keep getting errors:

CC              =       gcc -W -Wall -Werror

NAME            =       test

NAME2           =       test2

SRCS            =       sub/file1.c            \
                       开发者_StackOverflow社区 sub/file2.c            \
                        sub/file3.c            \
                        sub/file4.c

SRCS2           =      sub2/file1.c            \
                        sub2/file2.c            \
                        sub2/file3.c            \
                        sub2/file4.c

OBJS            =       $(SRCS:.c=.o)

OBJS2           =       $(SRCS2:.c=.o)

all:
    $(OBJS)
    $(CC) $(OBJS) -o $(NAME)

    $(OBJS2)
    $(CC) $(OBJS2) -o $(NAME2)                                                                          

Thank you, Ephismen.

[EDIT] Edited my problem My problem changed a bit. I need to compile in the same Makefile, always with the same rules, two different binaries. I tried following what worked for one but it doesn't seems to do right for two. If you have any advices please let me know.

The code posted works, but only compiles the first binary.

See this article:

Make Tutorial: How-To Write A Makefile

It explains everything including why not to use recursive make and how to do includes instead.

You'll especially want to read: Recursive Make Considered Harmful which explains why recursive make is bad and methods for avoiding it.

Use the following (remember to put tabs instead of spaces at beginnings of lines):

all: $(NAME) $(NAME2)

$(NAME): $(OBJS)
    $(CC) $(OBJS) -o $(NAME)

$(NAME2): $(OBJS2)
    $(CC) $(OBJS2) -o $(NAME2)