inputs without type in system verilog

I've encountered in an example for a system verilog code decleration of inputs and outputs for a module without stating their type, e.g log开发者_JAVA百科ic, wire...

module mat_to_stream (
  input [2:0] [2:0] [2:0] a,b,
  input newdata,
  input rst, clk,
  output [2:0] [7:0] A_out, B_out);
  ...rest of code...

What is the diffrence between stating logic and not stating any type?

There is no difference between stating logic and not stating any type.

input newdata,

is equivalent to

input logic newdata,

The SystemVerilog IEEE Std (1800-2009) describes this in section: "23.2.2.3 Rules for determining port kind, data type and direction".

It is very common to not assign inputs a data type, as they should almost always be wire.

input [7:0] newdata

Is nominally equivalent to:

input wire [7:0] newdata

It is actually picking up `default_nettype wire which could be changed to say uwire to enforce compiler checks for unique drivers, which will fail on wiring mistakes with multiple drives.

Using logic as a type allows the auto selection between wire and reg which is useful for outputs and allows easier refracting. Inputs can never be reg type.

Stuart Sutherlands SNUG2013 paper, section 12 covers how uwire could be used to better imply design intent if it was supported correctly by the tools.

From, SystemVerilog IEEE Std (1800-2017) describes this in section: "23.2.2.3 Rules for determining port kind, data type and direction"