I came across an atomic "fetch and store" instruction in the description of an MCS 开发者_如何学Clock.

From what I gather, this atomically writes a value to a memory location and returns the original value of that memory location, is that correct?

And is gcc's atomic builtin,

   __sync_lock_test_and_set

the same as an atomic fetch and store?

Per the GCC info page, this is indeed atomic, but it's not the basic atomic fetch and store.

(this is clipped from the 4.4 manual, so different section number)

5.48 Built-in functions for atomic memory access

(...)

TYPE __sync_fetch_and_add (TYPE *ptr, TYPE value, ...)
TYPE __sync_fetch_and_sub (TYPE *ptr, TYPE value, ...)
TYPE __sync_fetch_and_or (TYPE *ptr, TYPE value, ...)
TYPE __sync_fetch_and_and (TYPE *ptr, TYPE value, ...)
TYPE __sync_fetch_and_xor (TYPE *ptr, TYPE value, ...)
TYPE __sync_fetch_and_nand (TYPE *ptr, TYPE value, ...)
TYPE __sync_add_and_fetch (TYPE *ptr, TYPE value, ...)
TYPE __sync_sub_and_fetch (TYPE *ptr, TYPE value, ...)
TYPE __sync_or_and_fetch (TYPE *ptr, TYPE value, ...)
TYPE __sync_and_and_fetch (TYPE *ptr, TYPE value, ...)
TYPE __sync_xor_and_fetch (TYPE *ptr, TYPE value, ...)
TYPE __sync_nand_and_fetch (TYPE *ptr, TYPE value, ...)
bool __sync_bool_compare_and_swap (TYPE *ptr, TYPE oldval TYPE newval, ...)
TYPE __sync_val_compare_and_swap (TYPE *ptr, TYPE oldval TYPE newval, ...)
__sync_synchronize (...)
TYPE __sync_lock_test_and_set (TYPE *ptr, TYPE value, ...)
void __sync_lock_release (TYPE *ptr, ...)

They're apparently taken from the Intel Itanium reference manual, but GCC implements them on any CPU they can be (and warns if you use one on a CPU that doesn't, then uses a non-atomic version). The function you noted is actually an extended memory barrier (or critical area): the barrier is established by __sync_lock_test_and_set, and released by __sync_lock_release.

If you're looking for a basic atomic fetch-and-set, it's probably __sync_val_compare_and_swap although in most cases you'll want to use one of the more specific versions.