srand() analog for SystemVerilog

C rand() and srand() functions is very useful when you doing something like that:

srand(SEED);
for()
{
    //doing something with one thing using rand()
}
srand(SEED);
for()
{
    //doing something with other thing using rand()
}

Can I have something like this in SystemVerilog? Yeah, I know about $urandom(SEED)开发者_运维百科, but the thing is it should SRAND once and rand() then many times

Section 18.13.3 of the SystemVerilog IEEE Std (1800-2009) describes the srandom function. Chapter 18 has a code example showing how to use it with $urandom.

A lot of the randomization in SystemVerilog is generally done within classes, where SV has a powerful randomization infrastructure. You'd generally do something like this:

class Foo;
  rand int r_value;
  function void reseed(int seed);
    srandom(seed);
  endfunction
  function void do_something();  
    randomize();
    $display("something: %0d", value);
  endfunction
  function void do_something_else(); 
    randomize();
    $display("something: %0d", value);
  endfunction
endclass

....

Foo foo = new();
foo.reseed(seed);
foo.do_something();
foo.reseed(seed);
foo.do_something_else();

The advantage is that SV has a separate random number generator for every object, so that you're not changing the rest of the environment when you change that one object's seed. Of course, you can then also add constraints to r_value to make it fall between a range, for example.