What does 'processor synchronizes I/O instruction execution with external bus activity' mean?

The following excerpt is from Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 1: Basic Architecture (p.432, http://www.intel.com/Assets/PDF/manual/253665.pdf)

When the I/O address space is used instead of memory-mapped I/O, the situation is different in two respects:

• The processor never buffers I/O writes. Therefore, strict ordering of I/O operations is enforced by the processor. (As with memory-mapped I/O, it is possible for a chip set to post writes in certain I/O ranges.)

• The processor synchronizes I/O instruction execution with external bus activity (see Table 14-1).

Table 14-1. I/O Instruction Serialization

------------------+----------------------------------+----------------------------------
                  | Processor Delays Execution of …  | Until Completion of …
                  +---------------+----------开发者_开发百科--------+-----------------+----------------
Instruction Being | Current       | Next             |                 |
Executed          | Instruction?  | Instruction?     | Pending Stores? | Current Store?
------------------+---------------+------------------+-----------------+----------------
IN                |     Yes       |                  |      Yes        |
INS               |     Yes       |                  |      Yes        |
REP INS           |     Yes       |                  |      Yes        |
OUT               |               |       Yes        |      Yes        |       Yes
OUTS              |               |       Yes        |      Yes        |       Yes
REP OUTS          |               |       Yes        |      Yes        |       Yes
------------------+---------------+------------------+-----------------+----------------

Can anyone explain me what this table means? Especially, I have no idea what this 'pending stores' or 'current store' means.

The processor has a write queue, so when store something to memory, the data just goes into the queue. The instruction is considered complete as soon as the data goes into the queue -- you can start executing the next instruction without waiting for the data to go from the queue to the destination memory.

I/O space is not the same though. If you're reading from I/O space, your read won't even begin until all data in the memory write queue at that time has been written to memory. If you're writing to I/O space, the instruction starts to execute immediately, but the next instruction can't execute until all the data in the write queue has been written out and the data being written by the current instruction has been written.

The reason for this is fairly simple: when you're dealing with memory, the processor knows about all the address mapping, so if (for example) you write something to memory, and (almost) immediately read it back in, the processor can/will detect that the data is actually in the write queue, and and ensure that your read gets the current data.

With I/O space, however, the processor doesn't know how a read/write from/to a particular address might be related to a previous read/write in the memory space. For example, you might be sending some data to memory, and then telling your graphics card to use that data as a texture. You might not be as well, but the CPU has no real way to tell, so it has to make the pessimistic assumption, and wait for the data you wrote to memory to actually get there (or at least leave the CPU) before it tells the graphics card to use that data.