How to use $display without initial or always blocks

I'm trying to debug a Verilog module that doesn't use initial or always by using $di开发者_运维技巧splay statements. However, these appear to be illegal outside of initial or always blocks. Why is that? What are my alternatives?

Why? Because that's how the IEEE standard has specified it.

An alternative is to scope down into your module instance from your testbench. Your testbench will have an initial or always block which will call $display. Another useful system task is $monitor:

module tb;

reg a = 0;

dut dut ( .a(a) );

initial begin
    $monitor("time=%0t, a=%b, b=%b", $time, a, dut.b);
    #5 a = 1;
    #5 a = 0;
    #5 $finish;
end

endmodule

module dut (input a);
    wire b = ~a;
endmodule

You should get this kind of output when you run a simulation:

time=0, a=0, b=1
time=5, a=1, b=0
time=10, a=0, b=1

The dut.b signal is a hierarchical specifier that allows you to scope down into another module from the top-level module (tb). dut is the instance name, and b is the signal name inside the dut instance. A period separates the instance name from the signal name.