How to restart a Verilog simulation in Modelsim

I'm trying 开发者_如何学编程to debug a Verilog module. I find it tedious to have to stop a simulation, modify code, and then go through the process of starting the simulation again. Is there an easier way?

It's called restart :-) Simulate -> Run -> Restart

Here are my go-to one-liners for easy iterations:

To start your simulation and create your waveform:

vlog your_file.v; vsim work.your_TB; add wave -position insertpoint sim:/your_TB/*;

When updating code and testing new iterations:

vcom your_file.v; restart -f; run -A;

The ModelSim 'restart' command alone is not enough if design and/or testbench has changed, as it will just redraw the last simulation.

The design and testbench needs to be recompiled to account for all changes.

Typically design has not changed and you just want to run it against an updated testbench. In this case you can restart simulation by executing a custom script that you call with the 'do {script-name}' command whenever needed.

vlog -reportprogress 300 -work work testbench.v
restart -f
run 1us

Assumptions: testbench file = testbench.v; simulation time = 1us