How to produce different objects with the same file

I am trying to modify a Makefile, and I can't find the rule for that.

The following doesn't work. I don't know how t开发者_如何学Pythono write the src to obj rules.

# foo.c bar.c main.c
SRC = $(wildcard *.c)
OBJ_1 = $(patsubst %.c,%_1.o,$(SRC))
OBJ_2 = $(patsubst %.c,%_2.o,$(SRC))

GCC1 = vtcc
GCC2 = vtcc

LD_FLAGS= -lm -lpthread 

all: a1 a2

# executables :
a1: $(OBJ_1)
    $(GCC1) $(LDFLAGS) $^ -o $@
a2: $(OBJ_2)
    $(GCC2) $(LDFLAGS) $^ -o $@

# objects :
$(OBJ_1) : $(SRC)
    $(GCC1) -c $< -o $@

$(OBJ_2) : $(SRC)
    $(GCC2) -c $< -o $@

It's hard tell what your question is, but I think the last two rules should be:

# objects :
$(OBJ_1) : %_1.o : %.c
    $(GCC1) -c $< -o $@

$(OBJ_2) : %_2.o : %.c
    $(GCC2) -c $< -o $@